It is known that when a driver is to send a digital flow to a remote receiver through a transmission line there can be problems in the case in which there is no good match between transmission line impedance and the input and output impedances of the circuits connected therewith. Generally, in these cases there are power losses and multiple reflections which can cause an error probability increase in the symbol reception since, at a certain instant, in addition to the symbol transmitted at the given instant, there are present at the receiver, symbols transmitted in preceding time intervals and reflected by the line ends.
These disadvantages can be eliminated if at least the driver output impedance is rendered equal to the characteristic impedance of the line. In fact, even though there may be a mismatch at the output connected to the receiver, the input impedance of a rather long line is almost equal to the characteristic line impedance. That would result in a reflection at the far end of the line, but the reflected signal is absorbed at the input by the driver output impedance, whose value is equal to the line impedance, thus avoiding multiple reflections.
Under these conditions the receiver receives only the direct signal, whose signal width is doubled as an effect of overlapping between the direct signal and the signal immediately reflected, of course under the hypothesis that the receiver input impedance exceeds characteristic line impedance.
However, drivers with output impedance equal to the the characteristic impedance of the usual transmission lines are not easy to build, owing to unavoidable tolerances in fabricating process. Besides, the same transmission lines can have tolerances in the characteristic impedance. It is hence advisable to have an automatic system for adjusting the driver output impedance so as to obtain a good matching to the line, independent of fabrication tolerances and accidental circuit variations.
It is also convenient that the driver output impedance be made equal to the characteristic line impedance without using an external additional resistance, in order to avoid an oversizing of the output circuit with consequent speed loss and power consumption.
A solution to these problems has been described in the article entitled "A Self-Terminating Low-Voltage Swing CMOS Output Driver" by Thomas F. Knight et al, IEEE Journal of Solid State Circuits, Vol. 23, No. 2, April 1988.
In this system, the output impedance of a plurality of drivers contained in the same integrated circuit is controlled by a suitable circuit, also housed in the integrated circuit, comprising a driver, analogous to those controlled, and a receiver. The control driver sends a clock signal, locally-generated for this control purpose, on a transmission line length with the same characteristics as those of the lines connected to controlled-driver outputs. The line output is connected to the receiver input, that extracts from the received signal an enabling signal synchronized to logic-level transitions.
The voltage at the input of the reference line is read continuously by a threshold comparator, whereby it is compared with a threshold voltage of value equal to half the maximum value of the output voltage of the driver under matching conditions.
The information at the output of the comparator is considered valid, and can be used for control purposes, only at the instant when the receiver has detected a transition on the line after a delay slightly exceeding reference line propagating time, permitting the line voltage to stabilize at a level independent on a reflection coefficient value at the transmission end.
It is clear that in case of impedance matching between the driving line and the reference line the voltage at the line input, upon transmission of an edge, is equal to half the maximum value of the output voltage at the transmission end. That is why in this case (i.e. the case of matching) the comparator does not supply any output signal. However, if there is no matching, the information relevant to the algebraic difference with respect to threshold is used to vary a pulsed voltage across the terminals of a high-value capacitor, which is placed outside the integrated circuit. Therefore, the amplitude of this voltage varies as a function of the reflection coefficient at the reference line input.
A CMOS driver output impedance can be controlled by varying the gate voltage of the two transistors of the output stage within certain limits determined by the geometrical dimensions of the transistors themselves. To obtain this control, the predriver stages have to be fed with a suitable voltage, which in case of the approach described in the cited article is the pulsed voltage present at the external-capacity terminals. This voltage, besides matching the reference driver output impedance to the reference line, matches also the output impedance of all the other slaved drivers, being utilized to feed also all the other predriver stages.
If line voltage exceeds threshold voltage at the comparator input, the capacitor is continuously discharged by a power circuit, while in the opposite case the capacitor is charged and supplies current to all the predriver stages at the transition, up to the obtaining of an optimal value corresponding to the impedance matching condition.
However this circuit has a number of disadvantages. A first disadvantage is that during the initial adjusting phase at both line ends there is impedance mismatch, and hence there is a multiple reflection condition. As a consequence when a reflected edge goes back to the emitter to alter the line voltage level in the time interval in which the information is taken as valid, an error can be generated which places the circuit in an ambiguous adjustment condition.
Another disadvantage is due to threshold comparator response time, which must be much lower that the delay introduced by the reference transmission line, since when the receiver has detected the level transition for generating the signal enabling the reading of line voltage, the comparator output must be at the steady-state value. This delay, dependent on line length, is usually very small (of the order of ns) since the line is short. In addition, if a low error is desired, the differential voltage at the comparator inputs must very low and that implies a very sophisticated comparator.
Finally this circuit needs a large capacitor, which is not integratable and hence must be placed outside the integrated circuit. Also the driving of this capacitor needs power circuits, with consequent speed loss.